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Si5040
5.6. Clock and Data Recovery (CDR)
The Si5040 integrates a CDR to recover the clock and data from the input signal applied to RXDIN. The CDR can
be operated with or without an external reference clock. Reference or referenceless operation is programmed in
the RxCalConfig register (Register 8). If a reference clock is applied to the receiver, the CDR can be forced to lock
to the reference clock in the event that a loss of signal occurs. The CDR can be programmed to continue to sample
the RXDIN input while the receive PLL is locked to the reference clock. These options are controlled in the
RxConfig register (Register 7).
5.7. Reference Clock
The Si5040 will operate with or without an external reference clock. If a reference clock is applied, the receiver
uses the reference clock to center the internal VCO pull range, which, in turn, reduces the acquisition time of the
CDR. If the reference clock is not applied, the entire VCO frequency range will be swept for lock acquisition.
Note that since the applied reference clock is used for both the receiver and the transmitter and since the receiver
may be running at a different rate than the transmitter, the user is given the option of disabling the reference clock
on the receiver.
The RxrefclkEn bit in the RxConfig register (Register 7) controls this function. The receiver can be locked to the
reference clock under the following programmable conditions: (RxConfig, Register 7)
1. Set LTR (bit 1).
2. Set LTR on receive loss-of-signal (LOS) (bit 5).
Note: If it is desired to allow the CDR to acquire lock to the incoming data while LTR at Register 7, Bit 1 is set to 1 (Lock to Ref-
erence clock enabled), set CDRLTDATA at Register 7, Bit 4 to 1 (default). If it is desired to sample the incoming data with
a programmable phase and slice level while LTR is set to 1, set sliceEn[2:0] at Register 20 to 000 binary (auto slice dis-
abled).
5.8. Receiver Loss of Lock (LOL)
Receiver LOL functions differently depending on whether the receiver is operating in reference or referenceless
mode. By default (uselolmode Register 7, Bit 3 = 0), SQM-based LOL is used in referenceless mode, and
Frequency-based LOL is used in reference mode. In reference mode however, either SQM or Frequency LOL can
be used by setting Register 7, Bits 2 and 3 to the appropriate values.
5.8.1. SQM LOL
SQMLOL mode is selected in one of two ways. If register 7[3:2] = 11b, then SQMLOL mode is selected. If register
7[3] = 0 and register 7[1] = 0, then SQMLOL mode is selected. The SQMLOL method compares an internal jitter
measure to the sqmLOLThresh (see below on how to set this threshold). When the internal jitter measure is greater
than the sqmLOLThresh, RXLOL is asserted. When RxLOL is asserted the 5040 RX side will automatically start to
try to acquire lock again across an input data range of 9.8–11.4 Gbps. RxLOL is deasserted when the jitter
measure is less than the sqmLOLThresh. The sqmLOLThreshold must be set using registers 106, 107, 108, and
109 in the following order:
1. Write register 107 = A0h.
2. Write register 108 = 3Fh.
3. Write register 109 = B9h.
4. Write register 106 = 04h.
5. Write register 106 = 84h.
These are indexed address registers. Register 106 contains the sqmLOLThresh register address and 107-109
contain the data to be written to it. Register 106 must be written twice. The first write of 04h sets the address, and
84h applies the value in 107-109 into the sqmLOLThresh registers. The above values are recommended for all
applications.
Using sqmLOLThresh values other than the default or the one given above can cause unexpected problems, such
as false lock, and are not recommended.
24
Rev. 1.3
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